1. Field of the Invention
The present invention relates to a delay signal generating apparatus for generating a delay signal, and, in particular, to a delay signal generating apparatus used in a semiconductor testing apparatus.
2. Description of the Related Art
Development of semiconductor devices that can operate at high speed has recently flourished. This requires a semiconductor testing apparatus for testing such high-speed devices to have an ability to precisely control operation times. It is especially necessary to precisely delay a time at which an input pattern signal is input to a device to be tested with respect to a reference signal, depending on the input characteristics of the device to be tested.
FIG. 1 is a block diagram schematically showing a conventional variable delay circuit 10 that delays a reference signal 54 in order to generate a delay signal 74 having a predetermined delay time. The variable delay circuit 10 includes a minute variable delay portion 12, a gate stage number change portion 14, a linearizing memory 16, an input terminal 18 and an output terminal 20. The minute variable delay portion 12 includes a plurality of minute variable delay cells 12a, 12b, . . . , 12n. The gate stage number change portion 14 includes a plurality of variable delay elements 14a, 14b, 14c, . . . , 14m respectively having delay levels that change in a step-by-step manner. Each of the variable delay elements 14a, 14b, 14c, . . . , 14m has a gate circuit with one or more stages and a selector. In the conventional variable delay circuit 10, the reference signal 54 is input via the input terminal 18, and the delay signal 74 is output via the output terminal 20, after being delayed by a predetermined time period.
The gate stage number change portion 14 can change the delay time period by changing the number of gates through which the signal passes. Each of the variable delay elements 14a, 14b, 14c, . . . , 14m typically has resolution that is set for a delay of 200 (ps) or more. The minute variable delay portion 12 obtains a delay-setting resolution that is smaller than the delay time period of a single stage of a gate.
The linearizing memory 16 stores delay data that is combinations of delay elements that can realize predetermined delay times (delay time periods), respectively, in predetermined addresses therein. In the case of using one or some of the minute variable delay cells 12a, 12b, . . . , 12n and variable delay elements 14a, 14b, 14c, . . . , 14m for obtaining a certain delay time period, for example, corresponding bits of the linearizing memory 16 are set to xe2x80x9c1xe2x80x9d. Other bits, each corresponding to the minute variable delay cell or variable delay element are set to xe2x80x9c0xe2x80x9d. Each of the minute variable delay cells 12a, 12b, . . . , 12n and variable delay elements 14a, 14b, 14c, . . . , 14m selects whether to delay a signal input thereto based on the delay data supplied from the linearizing memory 16.
FIG. 2A is a circuit diagram illustrating a variable driving impedance type minute variable delay cell 12a. In FIG. 2A, Vdd denotes a positive power supply voltage and Vss denotes a negative power supply voltage. Either one of these power supply voltages can be used as ground. The delay data is supplied to a delay data terminal 26 from the linearizing memory 16 (see FIG. 1). The minute variable delay cell 12a can change the delay time period for the input signal depending on a logical value of the delay data. More specifically, the driving impedance is set low when the logical value of the delay data is xe2x80x9c0xe2x80x9d, while the driving impedance is set high when the logical value of the delay data is xe2x80x9c1xe2x80x9d. Thus, when the delay data has the logical value of xe2x80x9c1xe2x80x9d, the input signal input to an input terminal 22 is delayed more than when the delay data has the logical value of xe2x80x9c0xe2x80x9d, and is then output from an output terminal 24. The variable delay circuit 10 shown in FIG. 1 can achieve a delay-setting resolution from about 10 (ps) to about 100 (ps) by providing the minute variable delay portion 12 as described above and the gate stage number change portion 14.
FIG. 2B is a circuit diagram illustrating a variable load capacitance type minute variable delay cell 12a. The delay data is supplied to a delay data terminal 26 from the linearizing memory 16 (see FIG. 1). The minute delay cell 12a can change the delay time period for the input signal, depending on the logical value of the delay data. When the delay data has the logical value of xe2x80x9c1xe2x80x9d, the load capacitance is set. Thus, the input signal input to the input terminal 22 when the delay data has the logical value of xe2x80x9c1xe2x80x9d is delayed more than when the delay data has the logical value of xe2x80x9c0xe2x80x9d, and is output from the output terminal 24. The variable delay circuit 10 shown in FIG. 1 can achieve a delay-setting resolution from about 10 (ps) to about 100 (ps) by providing the minute variable delay portion 12 described above and the gate stage number change portion 14.
The conventional variable delay circuit 10 shown in FIG. 1 can be designed with a delay-setting resolution of 10 picoseconds or less, and several nanoseconds. In some cases, however, an error occurs between a designed delay time period and a delay time period actually provided by the delay element because of variation of self-heating of each delay element, change of ambient temperature, change in the power source voltage and the like.
FIG. 3 is a graph showing an example of delay characteristics of the variable delay circuit 10. An axis of abscissas represents a delay time set in the variable delay circuit 10 while an axis of ordinates represents the actual delay time achieved by the variable delay circuit. A line 30 represents ideal delay characteristics of the variable delay circuit 10. On the line of the ideal delay characteristics, the set delay time is equal to the actual delay time. A line 32 represents delay characteristics in a case where a propagation time period of the delay element is excessively long, while a line 34 represents delay characteristics in a case where the propagation time period of the delay element is excessively short.
Each of the lines 32 and 34 have errors with respect to the line 30. One of the errors is a gain error. Moreover, the lines 32 and 34 have discontinuous portions that are non-linear errors, as is apparent from the graph. This is because the variable delay elements included in the variable delay circuit 10 are a plurality of different types, therefore the effects on the results of the variation of the element characteristics, the temperature change and the like do not always coincide with each other.
In order to compensate for the non-linearity of the delay characteristics, a method for measuring the delay time periods provided by all the combinations of the delay elements is applied in advance, and the delay elements are then re-arranged so as to obtain a desired delay characteristic. The measured data is stored in the linearizing memory 16 (see FIG. 1) and used during the test of the semiconductor device, i.e., the device to be tested.
In this case, it is necessary to prepare in advance a delay circuit having redundancy, considering factors causing the errors such as variation of the element characteristics, the fluctuation of the temperature or the power source voltage. When all possible factors causing errors are considered, the variation of the characteristics of typical semiconductor devices is approximately xc2x130%. This means that a ratio of the longest delay time period of a semiconductor device to the shortest delay time period thereof is 1.86 (130/70), that is, approximately double. Therefore, in order to produce a variable delay circuit 10 having a predetermined resolution and variable widths under all conditions, a number of redundant circuits are required, resulting in an increase of the circuit scale as a whole. Moreover, a drift of the time may be caused by the fluctuation of the temperature or the power source voltage. This degrades timing precision.
Therefore, it is an object of the present invention to provide a delay signal generating apparatus that overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a delay signal generating apparatus for outputting a delay signal obtained by delaying a reference signal, includes: a phase shift device capable of outputting a plurality of shift signals having phases shifted from a phase of the reference signal by differing shift amounts, respectively; and a shift signal selector capable of selecting one of the shift signals that has a phase shifted by a predetermined shift amount and outputting the selected shift signal. Thus, the delay signal generating apparatus according to the first aspect of the present invention can output a delay signal having a predetermined delay time period by selecting a predetermined one of a plurality of shift signals.
In an embodiment of the present invention, a plurality of shift signal selectors are provided. The signal selectors can select one of the shift signals that have phases shifted by different shift amounts, respectively, and output a plurality of delay signals respectively having different delay time periods.
In another embodiment of the present invention, the phase shift device may be provided for each of the shift signal selectors.
In still another embodiment of the present invention, it is preferable that the phase shift device includes a plurality of phase shift elements that output a plurality of shift signals independently, by shifting the phase of the reference signal by the different shift amounts, respectively.
In still another embodiment of the present invention, the delay signal generating apparatus may further include a selection control signal supply portion capable of supplying to the shift signal selector a selection control signal for making the shift signal selector select one of the shift signals that is shifted by a predetermined amount.
In still another embodiment of the present invention, the delay signal generating apparatus further includes a shift amount setting portion capable of setting the shift amounts of the shift signals output from the plurality of phase shift elements.
In still another embodiment of the present invention, the shift signal selector may include: a multiplexer capable of selecting one of the shift signals that is shifted by a predetermined shift amount based on the selection control signal; a driver capable of outputting a delay signal based on an output of the multiplexer; and an additional circuit capable of applying to the multiplexer output a voltage of approximately a mid-point between two power supply voltages Vdd and Vss (Vdd greater than Vss) supplied to the driver.
In still another embodiment of the present invention, the shift signal selector may include: a multiplexer having a plurality of transmission gates to which the plurality of shift signals are input, and a summing portion which sums up outputs of the transmission gates on a point; and an additional circuit capable of applying to the summing portion in the multiplexer, a voltage of approximately mid-point between two power supply voltages Vdd and Vss supplied to the summing portion, wherein the multiplexer selects one of the shift signals shifted by the predetermined shift amount by making one of the plurality of transmission gates conductive based on the selection control signal.
In still another embodiment of the present invention, an additional circuit may be included that applies a voltage of approximately a mid-point between two power supply voltages Vdd and Vss (Vdd greater than Vss) to respective outputs of the plurality of phase shifted elements.
In still another embodiment of the present invention, the delay signal generating apparatus may further include: a reference phase shift element capable of outputting a reference delay signal delayed from the delay signal by a predetermined time period; a timing comparator capable of comparing timings of edges of the delay signal and edges of the reference delay signal and outputting a comparison result as a logical value xe2x80x9c0xe2x80x9d or a logical value xe2x80x9c1xe2x80x9d; and a measuring device capable of measuring a delay time period of the delay signal based on the comparison result by the timing comparator.
In still another embodiment of the present invention, the measuring device may include: an averaging portion capable of outputting an average value obtained by averaging the logical value output from the timing comparator at a predetermined period; and a determining portion capable of determining based on the averaged value, whether or not the delay time period of the delay signal is equal to the delay time period of the reference delay signal.
In still another embodiment of the present invention, the determining portion may determine that the delay time period of the delay signal is equal to the delay time period of the reference delay signal, when the averaged value of the logical value is 0.5.
In still another embodiment of the present invention, the delay signal generating apparatus may further include a shift amount adjusting portion, provided for each of the phase shift elements, capable of adjusting the shift amounts of the shift signals output from the plurality of phase shift elements, based on the determination result by the determining portion.
In still another embodiment of the present invention, the phase shift device may include: an oscillator capable of oscillating an oscillation signal having a period the same as that of the reference signal; a pulse insertion portion capable of generating an insertion pulse to be inserted to a referential oscillation signal having a front edge and a rear edge, at least one of which is synchronized with a front edge or a rear edge of the oscillation signal, and to insert the generated insertion pulse into the referential oscillation signal; and a delay phase-locked portion capable of generating one of the shift signals obtained by shifting a phase of the oscillation signal oscillated by the oscillator by a predetermined shift amount from a phase of the reference signal, based on a referential reference signal synchronized with the reference signal and having the same period as that of the referential oscillation signal and the referential oscillation signal with the insertion pulse inserted thereinto.
In still another embodiment of the present invention, the phase shift device may further include a phase comparator capable of outputting the referential reference signal and the referential oscillation signal based on a phase difference between a synchronized oscillation signal synchronized with the oscillation signal and a synchronized reference signal synchronized with the reference signal, and having the same period as that of the synchronized oscillation signal.
According to the second aspect of the present invention, a semiconductor test apparatus for testing a target device, includes: a pattern generator capable of generating, in synchronization with a reference signal, an input pattern signal to be input to the target device and an expected pattern signal to be output from the target device based on the input pattern signal; a delay pattern signal generator capable of generating a delay pattern signal delayed from the input pattern signal by a predetermined time period from a phase of the reference signal, depending on input characteristics of the target device; and a comparator capable of comparing an output pattern signal output from the target device based on the delay pattern signal, with the expected pattern signal. The delay pattern signal generator includes: a phase shift device capable of outputting a plurality of shift signals having phases shifted from the phase of the reference signal by different shift amounts, respectively; a shift signal selector capable of selecting one of the shift signals shifted by a predetermined shift amount and outputting a delay signal obtained by delaying the reference signal; and a delay pattern signal outputting portion capable of delaying the pattern signal delayed from the input pattern signal by the predetermined time period, based on the delay signal.
This summary of the invention does not necessarily describe all essential features so that the invention may also be a sub-combination of these described features.